Lead Verification Engineer

Cadence

3-6 years pre-silicon asic verification experience
Expertise in formal, sv/uvm, or ovm methodologies
Proficiency with eda tools like jasper, xcelium, imc
The role involves developing agentic AI solutions using LLMs to accelerate the pre-silicon design verification process

Job Summary

  • The role involves developing agentic AI solutions using LLMs to accelerate the pre-silicon design verification process.
  • Candidates will collaborate with highly skilled teams of machine learning engineers and software engineers to validate output correctness and efficiency.
  • Cadence offers a unique culture promoting collaboration, career development, and opportunities to work on cutting-edge technology.

Matching Summary

The role involves developing agentic AI solutions using LLMs to accelerate the pre-silicon design verification process.

Skills & Requirements

Must-have

  • 3-6 years pre-silicon ASIC verification experience
  • Expertise in Formal, SV/UVM, or OVM methodologies
  • Proficiency with EDA tools like Jasper, Xcelium, IMC
  • Strong programming skills in Verilog, SystemVerilog, Python

Nice-to-have

  • Experience with LLMs and ML technologies like RAG
  • Knowledge of RL and Agentic frameworks
  • Passion for leveraging AI to redefine verification
  • Ability to collaborate with machine learning engineers

Key Requirements

  • Bachelor's or master's degree in electrical or computer engineering
  • 3-6 years of experience in pre-silicon verification methodologies
  • Hands-on experience with industry standard EDA tools

Work Rights

Not specified

Tailored Resume

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