Job Summary

• The role involves defining and leading RTL development of a performance efficient CPU core.
• Candidates will explore high-performance strategies and perform microarchitecture development.
• Collaboration with a multi-functional engineering team is essential for validating design aspects.

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Skills & Requirements

Key Requirements

• Master’s with 8-11 years of experience
• PhD + 5-7 years of work experience
• knowledge of System Verilog, Verilog and/or VHDL

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