Asic Engineer || Sdc || Design And Timing Constraints | Exp 8+ Years

Cisco UK

Bangalore, India
Asic design and verification
Timing constraints development
Sdc/dta tools proficiency
Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms

Job Summary

  • Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms.
  • Collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.

Matching Summary

Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms.

Skills & Requirements

Must-have

  • ASIC design and verification
  • timing constraints development
  • SDC/DTA tools proficiency
  • fullchip SDC oversight
  • static timing analysis

Nice-to-have

  • collaboration with cross-functional teams
  • developing efficient methodologies
  • mentoring RTL design owners
  • AI era innovation

Key Requirements

  • Bachelors + 8 years experience
  • Masters + 6 years experience
  • PhD + 1 year experience
  • block/full chip SDC development
  • STA tools like PrimeTime/Tempus
  • Verilog/System Verilog programming

Work Rights

Not specified

Tailored Resume

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