Job Summary

• Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements.
• Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications.
• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Matching Summary

Salary

Base: $122,440.00-232,190.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Key Requirements

• Bachelor's Degree or Master's Degree
• 3+ years of experience (Bachelor's)
• 2+ years of experience (Master's)
• Digital logic experience
• VHDL/Verilog/System Verilog experience
• Testbench component development experience
• Design debugging skills
• Analog debug skills
• Real number simulation modeling

Work Rights