Dft Dv Engineer | 7+ Years | Dft/dv/uvm/system Verilog
Cisco UK
Bangalore, India
Dft verification
Test planning
System verilog testbench development
You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification
Job Summary
You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification.
Collaborate with the design/design-verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation and post silicon validation flows.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.
Matching Summary
You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification.
Skills & Requirements
Must-have
DFT verification
test planning
System Verilog testbench development
debugging DVE/Verdi
Tcl, Python/Perl scripting
Nice-to-have
UVM advanced System Verilog
JTAG protocol knowledge
scan architecture knowledge
MBIST knowledge
boundary scan knowledge
Key Requirements
8+ years of experience
Bachelor's or Master’s Degree in Electrical or Computer Engineering
DFT verification test plans and test benches
test planning based on complex design specification