Dft Engineer ( Testchip Architecture/ Rtl Dft)

GlobalFoundries

Not specified
Jtag, scan, memory bist, atpg
Systemverilog and uvm
Atpg and mbist tools (tessent)
GlobalFoundries is seeking a DFT Engineer to lead the architecture and methodology development for complex test-chip designs, focusing on BIST integration, validation, and post-silicon debug activities. The ideal candidate should possess extensive hands-on experience in DFT methodologies, including JTAG, MBIST, and ATPG, alongside strong scripting skills

Job Summary

  • We are seeking a skilled DFT Engineer to lead DFT architecture and methodology development for complex test‑chip designs.
  • The role involves defining and implementing Scan, MBIST, ATPG, and supporting post‑silicon debug activities.
  • GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets.

Matching Summary

Match Score: 85

GlobalFoundries is seeking a DFT Engineer to lead the architecture and methodology development for complex test-chip designs, focusing on BIST integration, validation, and post-silicon debug activities. The ideal candidate should possess extensive hands-on experience in DFT methodologies, including JTAG, MBIST, and ATPG, alongside strong scripting skills.

Skills & Requirements

Must-have

  • JTAG, Scan, Memory BIST, ATPG
  • SystemVerilog and UVM
  • ATPG and MBIST tools (Tessent)
  • Simulation, testbench development, debug
  • Post-silicon failure analysis, diagnostics
  • Tcl, Python, and Shell scripting

Nice-to-have

  • RTL development and functional verification
  • Cross-functional team collaboration
  • Strong communication skills

Key Requirements

  • 7+ years of hands-on experience
  • BSEE/MSEE or PhD in Electrical Engineering
  • Experience with ATE patterns and gate-level simulations

Work Rights

Not specified

Tailored Resume

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