Asic Engineering Technical Leader- Dft

Cisco

San Jose, California, United States
Base: $210,600.00 to $305,100.00; bonus/equity: no...
Design-for-test expertise
Post-silicon validation experience
Dft ip development
You will be in the Silicon One development organization as an ASIC Technical Lead in San Jose with a primary focus on Design-for-Test

Job Summary

  • You will be in the Silicon One development organization as an ASIC Technical Lead in San Jose with a primary focus on Design-for-Test.
  • You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era.

Matching Summary

You will be in the Silicon One development organization as an ASIC Technical Lead in San Jose with a primary focus on Design-for-Test.

Salary

Base: $210,600.00 to $305,100.00; Bonus/Equity: Not specified; Benefits: Medical, dental and vision insurance

Skills & Requirements

Must-have

  • Design-for-Test expertise
  • Post-silicon validation experience
  • DFT IP development

Nice-to-have

  • Verilog design experience
  • Functional verification skills
  • Innovative problem-solving

Key Requirements

  • Bachelor's or Master's Degree in Electrical or Computer Engineering
  • At least 10 years of experience
  • Prior experience with Jtag protocols

Work Rights

Not specified

Tailored Resume

Cover Letter