Asic Design Engineer

Cisco UK

San Jose, CA, USA
Base: $165,000.00 - $241,400.00; bonus/equity: not...
Onsite
Verilog/system verilog rtl design
High-performance asic subsystems
Timing closure, power optimization
Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks

Job Summary

  • Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks.
  • Contribute to the architecture and micro-architecture of high-performance ASIC subsystems for next-generation data center silicon.
  • U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance.

Matching Summary

Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks.

Salary

Base: $165,000.00 - $241,400.00; Bonus/Equity: Not specified; Benefits: Medical, dental, vision, 401(k) match, paid parental leave, disability, life insurance, stock units, paid time away

Skills & Requirements

Must-have

  • Verilog/System Verilog RTL design
  • High-performance ASIC subsystems
  • Timing closure, power optimization
  • ASIC design flows
  • Debug and problem-solving skills

Nice-to-have

  • Data center networking architectures
  • ARM-based SoC architectures
  • High-speed interface design
  • Engineering scripting and automation
  • Emulation or prototyping experience

Key Requirements

  • Bachelors + 7 years experience
  • Masters + 4 years experience
  • PhD + 1 year experience
  • One full ASIC tapeout experience
  • Advanced technology nodes experience

Work Rights

Not specified

Tailored Resume

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