Senior Design Verification Engineer

Cisco UK

Belgrade, Serbia
Systemverilog/uvm
Functional verification
Dv infrastructure implementation
Collaborate with us on functional verification using SystemVerilog/UVM, and take advantage of opportunities to engage in various development stages, from architectural discussions to emulation and simulation support

Job Summary

  • Collaborate with us on functional verification using SystemVerilog/UVM, and take advantage of opportunities to engage in various development stages, from architectural discussions to emulation and simulation support.
  • Our team blends experienced and energetic engineers, fostering collaboration and transparency in an environment built on trust.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.

Matching Summary

Collaborate with us on functional verification using SystemVerilog/UVM, and take advantage of opportunities to engage in various development stages, from architectural discussions to emulation and simulation support.

Skills & Requirements

Must-have

  • SystemVerilog/UVM
  • functional verification
  • DV infrastructure implementation
  • verification coverage
  • emulation support

Nice-to-have

  • collaboration and transparency
  • architectural discussions
  • scripting abilities
  • system integration knowledge
  • basic SW knowledge

Key Requirements

  • 5+ years experience
  • Advanced SystemVerilog and UVM knowledge
  • Advanced debug skills
  • System integration knowledge
  • Basic SW knowledge

Work Rights

Not specified

Tailored Resume

Cover Letter