Asic Verification Engineer - Cag - Taiwan, Taipei

Cisco UK

Taipei, Taiwan
System verilog and uvm
Asic verification process
Digital design and asic flow
Develop and maintain advanced test benches and verification environments using System Verilog and UVM

Job Summary

  • Develop and maintain advanced test benches and verification environments using System Verilog and UVM.
  • Execute the end-to-end verification process of complex ASIC design blocks.
  • Collaborate with cross-functional teams for thorough cross-block verification and top-level integration.

Matching Summary

Develop and maintain advanced test benches and verification environments using System Verilog and UVM.

Skills & Requirements

Must-have

  • System Verilog and UVM
  • ASIC verification process
  • Digital Design and ASIC flow

Nice-to-have

  • Eagerness to learn
  • Proactive problem-solving
  • Excellent team working skills
  • Self-driven mindset

Key Requirements

  • Bachelor's or Master's degree in EE or CE
  • 0-3 years of experience in ASIC verification
  • Proficiency in System Verilog-based verification

Work Rights

Not specified

Tailored Resume

Cover Letter