Silicon Packaging Design Engineer

Intel

Phoenix, Arizona, United States
Base: $105,650.00-149,150.00 usd; bonus/equity: st...
Microelectronic package or pcb physical layout design
Package design tools siemens xpedition cadence allegro
Substrate fit and routing studies
This role drives the end-to-end development of advanced substrate designs from concept through tape-out to ensure optimal performance and cost efficiency

Job Summary

  • This role drives the end-to-end development of advanced substrate designs from concept through tape-out to ensure optimal performance and cost efficiency.
  • The engineer will collaborate with cross-functional silicon and hardware teams to optimize pinout and package interactions for high-performance applications.
  • Intel offers a competitive total compensation package including stock bonuses, health benefits, retirement plans, and vacation time.

Matching Summary

This role drives the end-to-end development of advanced substrate designs from concept through tape-out to ensure optimal performance and cost efficiency.

Salary

Base: $105,650.00-149,150.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, and vacation programs

Skills & Requirements

Must-have

  • Microelectronic package or PCB physical layout design
  • Package design tools Siemens Xpedition Cadence Allegro
  • Substrate fit and routing studies
  • Design Rule Check (DRC) resolution
  • Cross-functional collaboration with silicon teams

Nice-to-have

  • Experience with electrical modeling simulation tools
  • Scripting skills in Python VB C languages
  • Package Layout Automation (PLA) experience
  • Strong analytical problem-solving debugging skills
  • Technology development in microelectronic packages

Key Requirements

  • Bachelor's degree with 1+ years experience OR Master's with 6 months experience
  • Electrical Engineering Mechanical Engineering or Material Sciences discipline
  • 6+ months experience in microelectronic package layout or manufacturing process

Work Rights

Not specified

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