Senior Digital Verification Engineer

NXP USA INC.

Pune, India
**
Systemverilog and uvm
Asic/ip verification
Test plans and testcases
** NXP USA INC. is seeking a Senior Digital Verification Engineer in Pune, India, with 6-10 years of experience in ASIC verification. The role involves leading verification efforts using SystemVerilog and UVM, contributing to low-power verification, and collaborating with design engineers to ensure product quality. **

Job Summary

  • Implement and execute verification for IP blocks and sub-systems using SystemVerilog and UVM, following established verification methodologies and plans.
  • Contribute to verification closure, analyzing coverage results, identifying gaps, and adding tests or coverage points to meet sign-off requirements.
  • Debug RTL issues, collaborating with design engineers to resolve functional mismatches, assertion failures, and coverage holes.

Matching Summary

Match Score: 75

** NXP USA INC. is seeking a Senior Digital Verification Engineer in Pune, India, with 6-10 years of experience in ASIC verification. The role involves leading verification efforts using SystemVerilog and UVM, contributing to low-power verification, and collaborating with design engineers to ensure product quality. **

Skills & Requirements

Must-have

  • SystemVerilog and UVM
  • ASIC/IP verification
  • test plans and testcases
  • verification closure
  • RTL issues debugging
  • regression execution

Nice-to-have

  • low-power verification
  • HW-FW co-verification
  • problem-solving skills
  • attention to detail

Key Requirements

  • 6 to 10 years of industry experience
  • at least one or more tape-out cycles
  • SystemVerilog and UVM proficiency
  • C/C++ programming exposure
  • Basic scripting skills
  • Git and Jira experience

Work Rights

Not specified

Tailored Resume

Cover Letter