Chip Level Sta Engineer

Cisco UK

Bachelor's or master's degree in electrical engineering
3 years of hands-on experience in asic design
Deep submicron cmos technologies knowledge
Join Cisco's ASIC Physical Design Team to ensure the highest quality in full-chip timing closure and circuit performance

Job Summary

  • Join Cisco's ASIC Physical Design Team to ensure the highest quality in full-chip timing closure and circuit performance.
  • Analyze full-chip timing and design rule violations to identify root causes and implement effective solutions for silicon excellence.
  • Develop robust timing closure methodologies for block and top-level designs to streamline development and improve efficiency.

Matching Summary

Join Cisco's ASIC Physical Design Team to ensure the highest quality in full-chip timing closure and circuit performance.

Skills & Requirements

Must-have

  • Bachelor's or Master's degree in Electrical Engineering
  • 3 years of hands-on experience in ASIC design
  • Deep submicron CMOS technologies knowledge
  • Full RTL2GDS flow experience
  • Floorplanning and power planning skills

Nice-to-have

  • Experience with standard cell timing characterization
  • Advanced understanding of timing derates and variations
  • Collaborative environment fostering mentorship
  • Innovation meeting precision culture

Key Requirements

  • Minimum 3 years of ASIC design and verification experience
  • Comprehensive knowledge of full design cycle from RTL to GDSII
  • Proven hands-on experience in RTL2GDS flows

Work Rights

Not specified

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