Dft Engineer

NVIDIA

Dft asic design and atpg/scan tools
Scan insertion flow ownership
Programming skills in scripting languages
Our Design-for-Test Engineering team at NVIDIA works on groundbreaking innovations involving creative solutions for DFT architecture, verification, and post-silicon validation on sophisticated semiconductor chips

Job Summary

  • Our Design-for-Test Engineering team at NVIDIA works on groundbreaking innovations involving creative solutions for DFT architecture, verification, and post-silicon validation on sophisticated semiconductor chips.
  • You will take full ownership of SCAN INSERTION projects from architecture and planning to implementation and verification while inventing and maintaining automation flows.
  • NVIDIA offers an exciting and educational environment where every individual significantly contributes to innovative products and achievements.

Matching Summary

Our Design-for-Test Engineering team at NVIDIA works on groundbreaking innovations involving creative solutions for DFT architecture, verification, and post-silicon validation on sophisticated semiconductor chips.

Skills & Requirements

Must-have

  • DFT ASIC Design and ATPG/SCAN tools
  • SCAN INSERTION flow ownership
  • Programming skills in scripting languages
  • Experience with DC/Fusion/Genus tools
  • Automation flow development for SCAN INSERTION

Nice-to-have

  • Knowledge of BIST and on-chip scan compression
  • Experience with Synopsis/Mentor SCAN tools
  • Programming in TCL, Perl, Python, Unix shell scripts
  • Proactive and self-motivated attitude
  • Sense of ownership and responsibility

Key Requirements

  • 0-2 years hands-on DFT/ATPG/SCAN experience
  • BSc. in Electrical Engineering or Computer Engineering

Work Rights

Not specified

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