Synthesis & Front-end Implementation Engineer

NXP Semiconductors

Pune, India
Rtl synthesis
Timing constraints (sdc)
Static timing analysis (sta)
You will be crucial in translating RTL designs into optimized gate-level netlists, ensuring performance, power, and area targets are met for complex IP blocks

Job Summary

  • You will be crucial in translating RTL designs into optimized gate-level netlists, ensuring performance, power, and area targets are met for complex IP blocks.
  • Responsibilities include performing synthesis, developing timing constraints, conducting STA, executing formal verification, and analyzing power and area.
  • The role requires collaboration with RTL designers, DFT engineers, and physical design engineers, as well as developing automation scripts and evaluating new CAD tools.

Matching Summary

You will be crucial in translating RTL designs into optimized gate-level netlists, ensuring performance, power, and area targets are met for complex IP blocks.

Skills & Requirements

Must-have

  • RTL synthesis
  • timing constraints (SDC)
  • Static Timing Analysis (STA)
  • Formal verification (LEC)
  • power consumption analysis
  • area estimation and optimization
  • Verilog/System Verilog

Nice-to-have

  • Design for Testability (DFT) principles
  • collaborative team environment
  • cross time zone collaboration

Key Requirements

  • 2+ years of relevant experience
  • Bachelor's or Master's degree
  • Proficiency with synthesis tools
  • Strong understanding of STA concepts
  • Experience with formal verification tools
  • Familiarity with scripting languages

Work Rights

Not specified

Tailored Resume

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