Director Of Engineering – Asic Design

NXP Semiconductors

Not specified
15+ years asic front-end design experience
Proven delivery of complex socs in production
Verilog/systemverilog rtl development skills
NXP Semiconductors is seeking a Director of Engineering to lead front-end design for advanced SoCs optimized for AI inference and edge compute workloads. The ideal candidate should possess extensive experience in ASIC design and leadership skills, with a strong emphasis on technical depth and system-level thinking

Job Summary

  • This role requires leading the front-end design of advanced SoCs optimized for AI inference, networking, and edge compute workloads.
  • The successful candidate will drive architectural trade-off analysis across compute, memory, interconnect, and I/O subsystems while ensuring first-silicon success.
  • You will build and mentor high-performing teams across RTL and integration while fostering a culture of engineering excellence and accountability.

Matching Summary

Match Score: 85

NXP Semiconductors is seeking a Director of Engineering to lead front-end design for advanced SoCs optimized for AI inference and edge compute workloads. The ideal candidate should possess extensive experience in ASIC design and leadership skills, with a strong emphasis on technical depth and system-level thinking.

Skills & Requirements

Must-have

  • 15+ years ASIC front-end design experience
  • Proven delivery of complex SoCs in production
  • Verilog/SystemVerilog RTL development skills
  • Microarchitecture optimization for AI inference
  • SoC/IP integration with ARM RISC-V PCIe
  • Functional verification strategy and coverage closure
  • Physical design collaboration for timing closure

Nice-to-have

  • Strong system-level thinking capabilities
  • Ability to influence across global organizations
  • Culture of engineering excellence and innovation
  • Experience with low-power design techniques
  • Mentoring and team-building leadership skills

Key Requirements

  • 15+ years of experience in ASIC front-end design
  • Proven delivery of complex SoCs or AI accelerators
  • Strong background in architecture RTL verification and timing
  • Expertise in Lint CDC/RDC STA and power analysis flows
  • Demonstrated ability to lead cross-functional global teams

Work Rights

Not specified

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