12-15 years pre-silicon asic verification experience
Formal, sv/uvm, and ovm methodology expertise
Hands-on experience with jasper, xcelium, imc tools
Cadence is seeking a Sr Principal Verification Engineer with a strong background in pre-silicon verification methodologies and a passion for integrating AI into the verification process. The ideal candidate will possess extensive experience in functional verification and collaborate with teams to innovate verification strategies using advanced machine learning techniques
Job Summary
The role involves developing agentic AI solutions using LLMs to accelerate the pre-silicon design verification process.
Candidates will collaborate closely with machine learning engineers to train large language models and validate output correctness.
Cadence offers a unique culture promoting collaboration across teams and multiple avenues for employee learning and development.
Matching Summary
Match Score: 85
Cadence is seeking a Sr Principal Verification Engineer with a strong background in pre-silicon verification methodologies and a passion for integrating AI into the verification process. The ideal candidate will possess extensive experience in functional verification and collaborate with teams to innovate verification strategies using advanced machine learning techniques.
Salary
Not specified; Not specified; Not specified
Skills & Requirements
Must-have
12-15 years pre-silicon ASIC verification experience
Formal, SV/UVM, and OVM methodology expertise
Hands-on experience with Jasper, Xcelium, IMC tools
Strong programming skills in Verilog, SystemVerilog, Python
Nice-to-have
Exposure to LLMs and ML technologies like RAG
Experience with Agentic frameworks and RL
Passion for leveraging AI to redefine verification
Ability to collaborate with ML engineering teams
Key Requirements
Bachelor's or master's degree in electrical or computer engineering
12-15 years of experience in formal or UVM verification
Proficiency in debugging using waveform viewers and simulation tools