Intern - Design Engineering

Cadence

Shanghai, China
Digital backend physical design
Static timing analysis (sta)
Layout and routing experience
The team delivers high-performance products using advanced technology nodes up to 6400MHz including TSMC 3nm and Samsung 4nm processes

Job Summary

  • The team delivers high-performance products using advanced technology nodes up to 6400MHz including TSMC 3nm and Samsung 4nm processes.
  • Interns will focus on high-speed digital DDR and HBM IP physical implementation while developing scripts to enhance the PD design flow.
  • Candidates must be able to work at least three days per week for an internship period of 6 to 8 months.

Matching Summary

The team delivers high-performance products using advanced technology nodes up to 6400MHz including TSMC 3nm and Samsung 4nm processes.

Skills & Requirements

Must-have

  • Digital backend physical design
  • Static timing analysis (STA)
  • Layout and routing experience
  • Physical verification skills
  • Scripting or tool development

Nice-to-have

  • PPA optimization methodologies
  • Strong problem-solving abilities
  • Team collaboration skills
  • Proactive attitude
  • Responsibility and ownership

Key Requirements

  • Master's degree in Microelectronics or Electrical Engineering
  • Proficiency with digital backend tools
  • Strong Chinese and English communication skills
  • Minimum 3 days per week availability
  • 6-8 month internship duration commitment

Work Rights

Not specified

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