Sr Principal Design Engineer

BETA CAE Systems International AG

Shanghai, China
Rtl design using verilog/systemverilog
Rtl verification tools and flows
Solid debugging experience/skills
Responsible for scheduling, designing, developing, and supporting IP models of system level memory

Job Summary

  • Responsible for scheduling, designing, developing, and supporting IP models of system level memory.
  • Perform as individual contributor for RTL design, verification, productizing, and documentation of memory IP.
  • Interface with internal and external customers to work on diverse problems and solutions related to emulation, simulation, or verification.

Matching Summary

Responsible for scheduling, designing, developing, and supporting IP models of system level memory.

Skills & Requirements

Must-have

  • RTL design using Verilog/SystemVerilog
  • RTL verification tools and flows
  • Solid debugging experience/skills
  • Memory IP design and verification

Nice-to-have

  • Emotionally intelligent collaborator and communicator
  • Team-wide collaboration tools and processes
  • Agile! Adaptive!
  • Cadence simulation and/or emulation products
  • Scripting languages like Perl, TCL, C-shell

Key Requirements

  • MSEE, or equivalent
  • Minimum of 5 years significant experience
  • Excellent communication skills (written and spoken English)

Work Rights

Not specified

Tailored Resume

Cover Letter