Principal Verification Engineer

BETA CAE Systems International AG

Shanghai, China
Uvm-based verification environments
Systemverilog and c++
Protocol requirements analysis
You will be responsible for scheduling, designing, developing, and supporting UVM-based verification environments, processes, and methodologies for IP models of system level memory

Job Summary

  • You will be responsible for scheduling, designing, developing, and supporting UVM-based verification environments, processes, and methodologies for IP models of system level memory.
  • Must analyze customer & vendor protocol requirements and execute on highly complex verification projects from requirements through delivery to post-delivery support.
  • Updating, enhancing, maintaining, and supporting existing system level UVM test environments for memory model products.

Matching Summary

You will be responsible for scheduling, designing, developing, and supporting UVM-based verification environments, processes, and methodologies for IP models of system level memory.

Skills & Requirements

Must-have

  • UVM-based verification environments
  • SystemVerilog and C++
  • protocol requirements analysis
  • complex digital systems verification
  • process automation scripting

Nice-to-have

  • collaborative working relationships
  • individual independent R&D skills
  • mentor less experienced engineers
  • cross-functional projects participation
  • high product quality maintenance

Key Requirements

  • BS/MS degree EE or CS
  • 5-7+ years of experience
  • Expert understanding of HDLs and HVLs
  • Solid experience in simulation/emulation
  • Expert working knowledge of EDA tools
  • Deep experience with UVM, SystemVerilog, and C++
  • Solid, deep experience on multiple protocols

Work Rights

Not specified

Tailored Resume

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