You will lead a team of backend engineers in delivering high-performance, low-power chip designs using cutting edge process technologies
Job Summary
You will lead a team of backend engineers in delivering high-performance, low-power chip designs using cutting edge process technologies.
This is a hands-on leadership role where you will shape physical implementation strategies and methodologies, drive execution, and ensure best-in-class KPIs for our next-generation wireless products.
Own and deliver physical signoff (STA, DRC, LVS, EMIR, IR-drop) with high quality and on schedule.
Matching Summary
You will lead a team of backend engineers in delivering high-performance, low-power chip designs using cutting edge process technologies.
Skills & Requirements
Must-have
physical design backend implementation
advanced node implementation methodologies
physical signoff STA DRC LVS
industry-standard EDA tools
hands-on leadership role
Nice-to-have
cutting edge process technologies
seamless integration and optimal performance
improve productivity and design quality
high-performing team of engineers
Key Requirements
10+ years of experience in physical design
at least 2 years in a technical leadership role
Proven track record of successful tapeouts in advanced FinFET nodes
B.Sc./M.Sc. in Electrical Engineering or related field