Sr. Principal Functional Verification Engineer: Applied Ml

Cadence Design Systems Inc.

Belo Horizonte, Minas Gerais, Brazil
Not specified; competitive benefits offered
10+ years experience in pre-silicon verification
Expertise in formal, sv/uvm, or ovm methodologies
Proficiency with eda tools like jasper, xcelium, imc
This role involves developing agentic AI solutions using Large Language Models to autonomously design and verify chips

Job Summary

  • This role involves developing agentic AI solutions using Large Language Models to autonomously design and verify chips.
  • The successful candidate will leverage advanced AI tools to architect and validate next-generation verification methodologies.
  • Cadence offers a collaborative culture focused on innovation, career development, and employee well-being within a Fortune 100 company.

Matching Summary

This role involves developing agentic AI solutions using Large Language Models to autonomously design and verify chips.

Salary

Not specified; Competitive benefits offered

Skills & Requirements

Must-have

  • 10+ years experience in pre-silicon verification
  • Expertise in Formal, SV/UVM, or OVM methodologies
  • Proficiency with EDA tools like Jasper, Xcelium, IMC
  • Strong programming skills in Verilog, SystemVerilog, Python
  • Advanced debugging using waveform viewers

Nice-to-have

  • Experience with LLMs and ML technologies like RAG
  • Knowledge of Agentic frameworks and RL
  • Ability to collaborate with ML engineering teams
  • Fluency in English and Portuguese
  • Proactive problem-solving and continuous learning mindset

Key Requirements

  • Bachelor's degree + 10 years OR MS + 7 years OR PhD + 5 years
  • 3+ years specific experience in ASIC verification methodologies
  • Bilingual proficiency in English and Portuguese required

Work Rights

Not specified

Tailored Resume

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