Dft Design Engineer

Intel

Bangalore, India
Hybrid
Dft design and rtl coding
Siemens tessent tool proficiency
4+ years dft experience
The role involves developing logic design and RTL coding while providing DFT timing closure support for various DFx content

Job Summary

  • The role involves developing logic design and RTL coding while providing DFT timing closure support for various DFx content.
  • Candidates must optimize logic to meet power, performance, area, timing, and test coverage goals for physical implementation.
  • The position requires collaborating with postsilicon and manufacturing teams to verify features on silicon and document learnings.

Matching Summary

The role involves developing logic design and RTL coding while providing DFT timing closure support for various DFx content.

Skills & Requirements

Must-have

  • DFT design and RTL coding
  • Siemens Tessent tool proficiency
  • 4+ years DFT experience
  • Power performance area optimization
  • ATE test content generation

Nice-to-have

  • Cross-functional collaboration skills
  • Strong problem-solving abilities
  • Drive innovation in methodologies
  • Passion for semiconductor tech
  • Continuous improvement mindset

Key Requirements

  • BTech in Electronics engineering with VLSI expertise
  • 4+ years of experience in DFT
  • Proficiency in Siemens Tessent, Spyglass, VC, Fusion compiler, VCS

Work Rights

Not specified

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