Sr Engineer Design Engineering - Sram Bit Cell Enablement
GlobalFoundries
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Cadence virtuoso
Drc and lvs verification
Spice simulation
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GlobalFoundries is seeking a Senior Engineer for SRAM bit cell enablement to support technology teams across various advanced semiconductor processes. The ideal candidate will have expertise in layout design, verification, and semiconductor technologies, particularly in SRAM functionality, and will collaborate with global teams.
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Job Summary
Support technology teams across 22 nm fully depleted SOI and 12 nm finfet technologies, involving bit cell layout, PDK enablement, and test structure verification.
Analyze incoming designs for bit cell content and maintain layout infrastructure for memory bit cells.
This role requires close cooperation with global internal teams and may involve interaction with customers and IP providers.
Matching Summary
Match Score: 75
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GlobalFoundries is seeking a Senior Engineer for SRAM bit cell enablement to support technology teams across various advanced semiconductor processes. The ideal candidate will have expertise in layout design, verification, and semiconductor technologies, particularly in SRAM functionality, and will collaborate with global teams.
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Skills & Requirements
Must-have
Cadence Virtuoso
DRC and LVS verification
SPICE simulation
semiconductor process flow
MOSFET device physics
SRAM bit cell functionality
Nice-to-have
scripting with R
high sigma simulations
customer interaction
Key Requirements
Master’s degree in microelectronics, electrical engineering, physics, or related fields
Experience in layout and design with Cadence Virtuoso
Familiar with scripting languages like Pearl, shell script, Python
Experience with SPICE simulation
Detailed knowledge about semiconductor process flow and technology
Good understanding of semiconductor device physics
Good understanding and experience with SRAM bit cell functionality