Soc Design Verification Engineer

Intel

Bangalore, India
Hybrid
System verilog and uvm methodology expertise
Transactor modelling and vip integration
Protocol experience with axi pcie ddr ucie
The role involves owning the verification lifecycle for one or more IPs/subsystems including requirements decomposition and signoff

Job Summary

  • The role involves owning the verification lifecycle for one or more IPs/subsystems including requirements decomposition and signoff.
  • Candidates must build reusable constrained-random and directed test scenarios while integrating industry-standard protocol VIPs.
  • This position is part of the Data Center Group committed to delivering exceptional Xeon-based and custom x86 products.

Matching Summary

The role involves owning the verification lifecycle for one or more IPs/subsystems including requirements decomposition and signoff.

Skills & Requirements

Must-have

  • System Verilog and UVM methodology expertise
  • Transactor modelling and VIP integration
  • Protocol experience with AXI PCIe DDR UCIe
  • Debugging skills using waveforms and tools
  • C/C++/Python proficiency for automation
  • X86/ARM architecture knowledge

Nice-to-have

  • Experience applying AI tools for verification
  • Strong communication and teamwork skills
  • Methodology improvement contributions

Key Requirements

  • Bachelor's/Master's in Electrical/Electronics/Computer Engineering
  • 5+ Years of Experience required
  • Proficiency with Synopsys VCS Cadence Xcelium Mentor Questa simulators

Work Rights

Not specified

Tailored Resume

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