Rtl Design Lead Hardware Engineer

Altera

Bengaluru, Karnataka, India
10+ years digital design experience
Vhdl verilog systemverilog expertise
Lead rtl design team responsibilities
The role involves leading a team to build soft IPs for Altera FPGAs including on-chip memory mapped interconnects and streaming protocols

Job Summary

  • The role involves leading a team to build soft IPs for Altera FPGAs including on-chip memory mapped interconnects and streaming protocols.
  • Engineers will develop new interconnect topologies to maximize data transfer throughput over long distances using hyperflex architectures.
  • The position requires close collaboration with software and embedded engineering teams to ensure design flows meet customer needs.

Matching Summary

The role involves leading a team to build soft IPs for Altera FPGAs including on-chip memory mapped interconnects and streaming protocols.

Skills & Requirements

Must-have

  • 10+ years digital design experience
  • VHDL Verilog SystemVerilog expertise
  • Lead RTL design team responsibilities
  • AXI APB AHB Avalon protocol knowledge
  • Timing closure and verification fundamentals

Nice-to-have

  • Quartus or Vivado tool flow knowledge
  • Tcl Perl Python scripting skills
  • Customer use case validation experience
  • ARM based bus protocols understanding
  • Strong written and oral communication

Key Requirements

  • BS/MS/PhD in Electrical Computer Software Engineering
  • 10+ years relevant industry experience
  • Strong digital design and timing closure knowledge

Work Rights

Not specified

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