Asic Design Verification Engineer

Cisco UK

Taipei, Taiwan
System verilog and uvm methodology
Asic design and verification flow
Uvm/systemverilog testbenches
You will be developing the ASICs at the heart of Cisco's next generation switching systems

Job Summary

  • You will be developing the ASICs at the heart of Cisco's next generation switching systems.
  • You will collaborate closely with the design team and the hardware team to verify the ASIC in simulation, in emulation and during ASIC bring up.
  • Cisco is revolutionizing how data and infrastructure connect and protect organizations in the AI era and beyond.

Matching Summary

You will be developing the ASICs at the heart of Cisco's next generation switching systems.

Skills & Requirements

Must-have

  • System Verilog and UVM methodology
  • ASIC design and verification flow
  • UVM/SystemVerilog testbenches
  • constrained random DV environments
  • end-to-end verification

Nice-to-have

  • collaborative and team-focused
  • drive to learn and grow
  • knowledge on high speed Ethernet protocol

Key Requirements

  • Bachelor’s or master’s degree in EE and CE
  • Hands-on experience on System Verilog and UVM
  • Good Scripting experience (Python, Perl, TCL, shell programming)

Work Rights

Not specified

Tailored Resume

Cover Letter