Principal Engineer, Process Development Engineering

Analog Devices Foundation

Limerick, Ireland
Chip-level and ip-level esd protection design
Esd, eos, and latch-up (lup) methodologies
Circuit simulation and interconnect parasitic extraction
Lead chip-level and IP-level ESD protection design, simulation, and verification to meet product ESD robustness requirements

Job Summary

  • Lead chip-level and IP-level ESD protection design, simulation, and verification to meet product ESD robustness requirements.
  • Define ESD, EOS, and Latch-up (LUP) methodologies for silicon development and customize verification tools.
  • Conduct failure and root cause analysis for ESD robustness issues and mentor junior engineers on ESD principles.

Matching Summary

Lead chip-level and IP-level ESD protection design, simulation, and verification to meet product ESD robustness requirements.

Skills & Requirements

Must-have

  • chip-level and IP-level ESD protection design
  • ESD, EOS, and Latch-up (LUP) methodologies
  • circuit simulation and interconnect parasitic extraction
  • Transmission Line Pulse device/product measurement
  • semiconductor physics, CMOS, FinFet, and ESD/EOS protection device design

Nice-to-have

  • technical interface between design teams, foundries, and reliability teams
  • open to challenges, strong initiative, independent worker
  • documentation and publication of best practices

Key Requirements

  • Bachelor's (10+ years), Master's (8+ years), or PhD (5+ years) in Electrical Engineering
  • Coursework and/or experience with integrated circuit design
  • Solid understanding of device physics
  • Background in ESD protection circuit design techniques
  • Experience with Cadence, Virtuoso, and PERC tools
  • Familiarity with ESD simulation tools and techniques
  • Understanding of HBM, CDM and IEC-61000-4-2 ESD models

Work Rights

Export licensing review process may apply

Tailored Resume

Cover Letter