Senior Design Verification Engineer

Intel Corporation

Bangalore, India
Verification planning and execution
Scalable verification environments
Interconnects and bus protocols
Independently own verification of interconnect and chassis IP blocks from planning through coverage closure, operating with minimal guidance

Job Summary

  • Independently own verification of interconnect and chassis IP blocks from planning through coverage closure, operating with minimal guidance.
  • Build scalable verification environments with reusable testbenches, checkers, constrained-random tests, and debug infrastructure.
  • Collaborate closely with architecture, design, and software teams on spec reviews, feature clarification, bug triage, and closure.

Matching Summary

Independently own verification of interconnect and chassis IP blocks from planning through coverage closure, operating with minimal guidance.

Skills & Requirements

Must-have

  • verification planning and execution
  • scalable verification environments
  • interconnects and bus protocols
  • simulation-based verification methodologies
  • hands-on coding proficiency
  • AI-assisted development tools

Nice-to-have

  • mentoring junior engineers
  • formal verification tools experience
  • emulation or FPGA verification
  • RTL concepts knowledge

Key Requirements

  • 8-12 years of relevant experience
  • BS/MS in Electrical Engineering, Computer Science, or related field
  • IP-level DV with subsystem-level verification exposure
  • SystemVerilog/UVM, C/C++, and Python proficiency
  • Comfort using AI-assisted development tools

Work Rights

Not specified

Tailored Resume

Cover Letter