Senior Staff/staff Design Verification Engineer

Silicon Labs

Hybrid
System verilog
Uvm
Digital ams cosimulation
Silicon Labs is seeking a Senior Staff/Staff Design Verification Engineer to join their IoT Digital team, focusing on the verification of complex digital designs involving analog and mixed-signal components. The ideal candidate will have significant experience in System Verilog and UVM methodologies, working in a hybrid environment

Job Summary

  • The IoT Digital team is responsible for the architecture specification, design, verification, and implementation of world-class Wireless MCU SoCs.
  • Develop and maintain a cosimulation environment for seamless verification between digital RTL and analog/mixed-signal models.
  • You can look forward to benefits including Employee Stock Purchase Plan (ESPP) and insurance plans with Outpatient cover.

Matching Summary

Match Score: 85

Silicon Labs is seeking a Senior Staff/Staff Design Verification Engineer to join their IoT Digital team, focusing on the verification of complex digital designs involving analog and mixed-signal components. The ideal candidate will have significant experience in System Verilog and UVM methodologies, working in a hybrid environment.

Skills & Requirements

Must-have

  • System Verilog
  • UVM
  • Digital AMS Cosimulation
  • Testbench Development
  • Complex Verification Environments

Nice-to-have

  • Python or Perl scripting
  • Industry-standard interfaces knowledge

Key Requirements

  • 10-15 years of industry experience
  • Master’s or Bachelor’s Degree in Computer Science, Electrical Engineering, Computer Engineering, or related fields
  • Assertion-based Formal Verification proficiency
  • Familiarity with Verilog, Verilog A, C, and TCL
  • Tools proficiency in Xcelium, Spectre, Questasim, Symphony

Work Rights

Not specified

Tailored Resume

Cover Letter