Principal Firmware Engineer

Cadence

Ddr5 jedec spec knowledge
Bare-metal c programming on microcontrollers
High-speed serdes or memory interface experience
The role involves developing firmware for DDR5 PHY using microcontrollers within the Cadence DDR PHY IP Front End Design team

Job Summary

  • The role involves developing firmware for DDR5 PHY using microcontrollers within the Cadence DDR PHY IP Front End Design team.
  • Candidates will collaborate with hardware designers and memory subsystem architects to derive and implement training algorithms.
  • Responsibilities include debugging firmware in RTL-based simulations and performing silicon bring-up on test boards.

Matching Summary

The role involves developing firmware for DDR5 PHY using microcontrollers within the Cadence DDR PHY IP Front End Design team.

Skills & Requirements

Must-have

  • DDR5 JEDEC spec knowledge
  • Bare-metal C programming on microcontrollers
  • High-speed SerDes or Memory interface experience
  • RTL simulation debugging with firmware
  • Shell/Perl/Python/TCL scripting skills

Nice-to-have

  • Collaboration with hardware designers
  • Experience with verification EDA tools
  • Silicon bring-up board debugging
  • Low-level API development
  • Memory subsystem architecture understanding

Key Requirements

  • Good Knowledge of DDR5 JEDEC spec
  • Relevant experience in bare-metal firmware development
  • Comfortable debugging RTL simulations involving firmware

Work Rights

Not specified

Tailored Resume

Cover Letter