Principal Logic Design Engineer

Altera

New Delhi, India
Fully remote
15+ years experience in electrical engineering
System verilog and vcs simulator expertise
Rtl coding and logic optimization skills
The role involves developing and optimizing mixed-signal and high-speed IPs for integration into full-chip designs

Job Summary

  • The role involves developing and optimizing mixed-signal and high-speed IPs for integration into full-chip designs.
  • Candidates will participate in the entire IP development flow, including RTL coding, simulation, and hardware brings up.
  • The position requires a deep understanding of Altera's programmable solutions to drive innovation in AI acceleration and data infrastructure.

Matching Summary

The role involves developing and optimizing mixed-signal and high-speed IPs for integration into full-chip designs.

Skills & Requirements

Must-have

  • 15+ years experience in electrical engineering
  • System Verilog and VCS simulator expertise
  • RTL coding and logic optimization skills
  • C/C++/Perl/Python/TCL scripting proficiency
  • IP block integration and release process

Nice-to-have

  • FPGA design and programming experience
  • RTL validation background
  • Strong communication and problem-solving skills
  • Experience with cell libraries and functional units

Key Requirements

  • Bachelor's or Master's degree in Electrical Engineering
  • 15+ years of professional experience required
  • Proficiency in Lint and Synthesis tools

Work Rights

Not specified

Tailored Resume

Cover Letter