Senior Asic Design Verification Infrastructure And Tools Engineer – Gpu

Nvidia Corporation

CA, United States
Base: 136,000 usd - 218,500 usd (level 3); 168,000...
On-site
High-speed io verification flows
Continuous integration system
Python, perl, or other systems programming language
NVIDIA is seeking a Senior ASIC Design Verification Engineer specializing in tools and automation to enhance the efficiency of its High-Speed IO engineering teams. The ideal candidate will have significant experience in ASIC design verification methodologies and programming skills, contributing to cutting-edge technology across various product lines

Job Summary

  • Improve the speed, flexibility, and extensibility of the High-Speed IO front end integration, build, and verification flows.
  • Keep the High-Speed IO Continuous Integration system at the cutting edge of industry techniques.
  • Deploy tracking metrics to resolve operational issues, drive forecasting, and improve design productivity.

Matching Summary

Match Score: 85

NVIDIA is seeking a Senior ASIC Design Verification Engineer specializing in tools and automation to enhance the efficiency of its High-Speed IO engineering teams. The ideal candidate will have significant experience in ASIC design verification methodologies and programming skills, contributing to cutting-edge technology across various product lines.

Salary

Base: 136,000 USD - 218,500 USD (Level 3); 168,000 USD - 264,500 USD (Level 4); Bonus/Equity: Equity; Benefits: Benefits

Skills & Requirements

Must-have

  • High-Speed IO verification flows
  • Continuous Integration system
  • Python, Perl, or other Systems Programming language
  • Object Oriented Programming with SystemVerilog
  • Make based build systems
  • Continuous Integration pipelines

Nice-to-have

  • AI to solve problems
  • Agentic AI flows
  • Strong verification mindset

Key Requirements

  • Bachelors or Masters degree (or equivalent experience)
  • 5+ years of relevant industry experience
  • Exposure to computer architecture, ASIC design, and verification methodology
  • Experience with verification methodology (UVM or similar)
  • Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi interactive, Debussy, GDB)
  • Experience with Make based build systems in large, distributed computing environments
  • Tenacity to root cause and fix Infrastructure problems

Work Rights

Not specified

Tailored Resume

Cover Letter