Design For Test Engineer Iv (ic)

Arrow Electronics Inc

San Jose, CA, United States
Base: $112,200.00 - $170,500.00; bonus/equity: not...
On-site
Dft implementation for 3nm and 5nm networking chips
Scan-insertion using tessent testkompress
Atpg pattern generation with mentor tessent
Implement DFT for advanced Networking chips and IP cores, utilizing industry-leading tools for scan insertion and ATPG

Job Summary

  • Implement DFT for advanced Networking chips and IP cores, utilizing industry-leading tools for scan insertion and ATPG.
  • Perform comprehensive pattern simulations and debug complex mismatches, ensuring high-quality chip testing.
  • Arrow Electronics offers competitive compensation, a solid benefits package including medical, dental, vision, 401k with matching, and growth opportunities.

Matching Summary

Implement DFT for advanced Networking chips and IP cores, utilizing industry-leading tools for scan insertion and ATPG.

Salary

Base: $112,200.00 - $170,500.00; Bonus/Equity: Not specified; Benefits: Medical, Dental, Vision Insurance, 401k, With Matching Contributions, Short-Term/Long-Term Disability Insurance, Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options, Paid Time Off, Tuition Reimbursement

Skills & Requirements

Must-have

  • DFT implementation for 3nm and 5nm Networking chips
  • Scan-Insertion using Tessent TestKompress
  • ATPG pattern generation with Mentor Tessent
  • Pattern Simulation using VCS
  • Mismatch debug using Verdi
  • MBIST Insertion and Verification
  • IEEE 1149.1 JTAG Insertion and verification

Nice-to-have

  • DFT flow enhancement/automation
  • Low power DFT
  • Excellent communicator

Key Requirements

  • 5 – 7 Years of experience in DFT
  • Worked on multi-million gate count SoCs
  • B. Tech, M.Tech in Microelectronics/Electronics

Work Rights

Not specified

Tailored Resume

Cover Letter