Asic Verification Engineer - Pmu

Invidia

Shanghai, China
Uvm based unit-level tb
System verilog experience
Ic background
Power efficiency is critical across all NVIDIA products

Job Summary

  • Power efficiency is critical across all NVIDIA products.
  • The PMU IP is crucial in optimizing chip performance and efficiency.
  • We are seeking a Senior Verification Engineer to enhance our PMU engine.

Matching Summary

Power efficiency is critical across all NVIDIA products.

Skills & Requirements

Must-have

  • UVM based unit-level TB
  • System Verilog experience
  • IC background

Nice-to-have

  • Good communication skills
  • Experience in building complex TB
  • Problem-solving skills

Key Requirements

  • BS with 4+ years experience
  • MS with 2+ years experience
  • Fluent in English

Work Rights

Not specified

Tailored Resume

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