Senior Digital/ams Validation And Integration Engineer

NXP USA INC.

San Jose, California, US
Base: $166,200 to $228,500 annually; bonus/equity:...
Rtl design in verilog/systemverilog
Timing closure and synthesis
Silicon validation with python tools
The role involves driving the integration of complex digital logic into Automotive SerDes transceivers

Job Summary

  • The role involves driving the integration of complex digital logic into Automotive SerDes transceivers.
  • You will own the path from RTL through timing closure and support validation in the lab.
  • NXP offers competitive benefits including health insurance, 401(k), and paid leave.

Matching Summary

The role involves driving the integration of complex digital logic into Automotive SerDes transceivers.

Salary

Base: $166,200 to $228,500 annually; Bonus/Equity: Not specified; Benefits: health, dental, and vision insurance, 401(k), paid leave

Skills & Requirements

Must-have

  • RTL design in Verilog/SystemVerilog
  • Timing closure and synthesis
  • Silicon validation with Python tools

Nice-to-have

  • Experience with Automotive Ethernet standards
  • Knowledge of DFT and BIST insertion
  • Familiarity with high-speed Analog Front Ends

Key Requirements

  • BSEE/MSEE with 5–8+ years of experience
  • Advanced proficiency in SystemVerilog/Verilog
  • Strong understanding of Static Timing Analysis

Work Rights

Not specified

Tailored Resume

Cover Letter