Design Engineer (7425)

TSMC

San Jose, CA, US
$156,853 pyear to $157,200pyear
On-site
Vlsi design
Digital integrated circuits
Physical design
Responsible for the Design Rule Check, Layout vs. Schematic checking and fix all PDV/EMIR/Noise/SigEM violations and errors

Job Summary

  • Responsible for the Design Rule Check, Layout vs. Schematic checking and fix all PDV/EMIR/Noise/SigEM violations and errors.
  • Conduct customization and implementation of top clocks and implement timing ECOs on high performance blocks.
  • TSMC’s total compensation package consists of market competitive pay, allowances, bonuses, and comprehensive benefits.

Matching Summary

Responsible for the Design Rule Check, Layout vs. Schematic checking and fix all PDV/EMIR/Noise/SigEM violations and errors.

Salary

$156,853 /year to $157,200/year

Skills & Requirements

Must-have

  • VLSI design
  • digital integrated circuits
  • physical design
  • design verification
  • EDA tools/design flows
  • Netlist-GDS P&R
  • timing closure

Nice-to-have

  • hardware design knowledge
  • computer architecture
  • data analysis skills

Key Requirements

  • Master’s degree in Electrical Engineering or related
  • One (1) year of related experience
  • Experience in Perl/TCL programming
  • Experience reviewing timing paths for DFT

Work Rights

Not specified

Tailored Resume

Cover Letter