Sr Principal Design Engineer

BETA CAE Systems International AG

Bangalore, India
Uvm-based verification environments
Systemverilog and uvm methodology
Debugging complex ip designs
Develop and maintain UVM-based verification environments for IP-level verification

Job Summary

  • Develop and maintain UVM-based verification environments for IP-level verification.
  • Mentor and guide junior engineers in verification best practices.
  • Work on cutting-edge IP technologies for next-generation SoCs.

Matching Summary

Develop and maintain UVM-based verification environments for IP-level verification.

Skills & Requirements

Must-have

  • UVM-based verification environments
  • SystemVerilog and UVM methodology
  • debugging complex IP designs
  • testbench development
  • simulation and regression strategies

Nice-to-have

  • SERDES verification experience
  • UCIe protocol familiarity
  • chiplet integration knowledge
  • high-speed interfaces verification

Key Requirements

  • Minimum 10 years of experience in IP verification
  • Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field

Work Rights

Not specified

Tailored Resume

Cover Letter