Responsible for the development and delivery of IO IPs (GPIO, LVDS, SSTL, HSTL, MIPI, etc) in multiple technology nodes and achieving corresponding PPA indicators
Job Summary
Responsible for the development and delivery of IO IPs (GPIO, LVDS, SSTL, HSTL, MIPI, etc) in multiple technology nodes and achieving corresponding PPA indicators.
Collaborate in the design and implementation of test chips, packaging design, test board design, post-silicon testing, and qualification.
GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce.
Matching Summary
Responsible for the development and delivery of IO IPs (GPIO, LVDS, SSTL, HSTL, MIPI, etc) in multiple technology nodes and achieving corresponding PPA indicators.
Skills & Requirements
Must-have
CMOS design
Analog/IO IP development
IO IP development
RTL design (Verilog/VHDL)
ESD, pad ring design
physical verification flows
Nice-to-have
solution-oriented approach
culture of innovation
low-power design techniques
IO reliability
Key Requirements
3+ years of experience in semiconductor IP design
Bachelor's or master's degree in Electronics engineering