Sr. Asic Engineer (uvm | System Verilog | Scripting) - 8+ Yrs , Blr

Cisco UK

Blr, India
Uvm verification methodology
System verilog proficiency
Block and top-level dv environment
The role involves architecting and developing sophisticated ASIC verification environments for Cisco's Silicon One architecture

Job Summary

  • The role involves architecting and developing sophisticated ASIC verification environments for Cisco's Silicon One architecture.
  • Candidates will lead the ASIC bring-up process and collaborate with multi-functional teams to ensure seamless integration.
  • This position offers exposure to all aspects of systems including silicon, hardware, software, telemetry, and security.

Matching Summary

The role involves architecting and developing sophisticated ASIC verification environments for Cisco's Silicon One architecture.

Skills & Requirements

Must-have

  • UVM verification methodology
  • System Verilog proficiency
  • Block and top-level DV environment
  • Constraint random stimulus development
  • Gate Level Simulation experience

Nice-to-have

  • Perl or Python scripting skills
  • Veloce emulation platform experience
  • Formal verification knowledge
  • PCIe Ethernet protocol expertise
  • Post-silicon bring-up leadership

Key Requirements

  • Bachelor's Degree in EE or CE
  • 7+ years of ASIC design verification experience
  • Hands-on experience building test benches from scratch

Work Rights

Not specified

Tailored Resume

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