Senior Ip Logic Design Engineer

Intel

Santa Clara, California, United States
Base: $190,610.00-269,100.00 usd annually; bonus/e...
Hybrid
10+ years in soc design
Memory coherency protocol expertise
Rtl coding in verilog or systemverilog
The role involves architecting scalable memory coherency protocols and interconnect topologies for high-performance data center and AI SoCs

Job Summary

  • The role involves architecting scalable memory coherency protocols and interconnect topologies for high-performance data center and AI SoCs.
  • Candidates will collaborate with cross-functional teams including physical design, software, and firmware to ensure seamless integration of memory fabric systems.
  • Intel offers a competitive total compensation package including stock bonuses, health benefits, retirement plans, and vacation time.

Matching Summary

The role involves architecting scalable memory coherency protocols and interconnect topologies for high-performance data center and AI SoCs.

Salary

Base: $190,610.00-269,100.00 USD annually; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, and vacation programs

Skills & Requirements

Must-have

  • 10+ years in SoC design
  • Memory coherency protocol expertise
  • RTL coding in Verilog or SystemVerilog
  • Interconnect technology knowledge
  • Simulation tools proficiency

Nice-to-have

  • Experience with HBM or DDR technologies
  • AI/ML accelerator design background
  • Python or TCL scripting skills
  • Software-hardware co-design experience
  • Mentoring junior engineers

Key Requirements

  • MS/PhD in Electrical or Computer Engineering
  • Minimum 10 years of SoC design experience
  • Expertise in MESI, MOESI, CXL, CCIX, or CHI protocols
  • Proficiency with EDA tools for synthesis and timing analysis

Work Rights

Not specified

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