This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols
Job Summary
This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols.
The candidate will contribute to digital architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding for all IPs in the SerDes physical IP portfolio as well as executing various tool flows for IP quality control.
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Matching Summary
This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols.
Skills & Requirements
Must-have
Digital Design and Architecture
digital RTL implementation
low power designs
synthesis and timing analysis
Serial standards (PCIE, USB, Ethernet)
Nice-to-have
cross-functional communication skills
collaboration with worldwide geographies
scripting for design automation
familiarity with uC Based subsystems
Key Requirements
7+ Years’ experience in Digital Design
Bachelor's Degree (MSEE Preferred)
Proven experience in Design Architecture
Proven experience in Design implementation
Proven experience in Embedded uC Designs
Proven experience in Synthesis and SDC Creation
Proven experience in Debugging verification test cases