This is a unique opportunity for bringing timing & convergence for SOC, driving the design changes, while being responsible for end2end timing closure and timing signoff
Job Summary
This is a unique opportunity for bringing timing & convergence for SOC, driving the design changes, while being responsible for end2end timing closure and timing signoff.
Expected Interface with critical domains like IP, Functional Integration, DFT & Verification while working closely with Physical implementation team for providing feedback, timing convergence and ECO creation.
Hands-on experience of working on technology nodes like 28nm, 16nm, 10nm, 7nm and good knowledge of EDA tools from RC, DC, PT, PTSI.
Matching Summary
This is a unique opportunity for bringing timing & convergence for SOC, driving the design changes, while being responsible for end2end timing closure and timing signoff.
Skills & Requirements
Must-have
end2end timing closure and signoff
timing signoff criteria ownership
design clocking and constraints development
SOC IO constraints development
Advance Timing Analysis and Debug
ECO creation with signal integrity & EM/IR
working on technology nodes 28nm to 7nm
EDA tools from RC, DC, PT, PTSI
Nice-to-have
understanding advanced digital design architectures
scripting for design implementation flow
Key Requirements
Experienced STA Leader
Ownership for driving timing signoff criteria
Expertise in SOC IO constraints developments
Expertise in Advance Timing Analysis, Debug and timing convergence
Hands-on experience on technology nodes 28nm, 16nm, 10nm, 7nm