Apple is seeking an experienced Asic Design Engineer to work on high-performance cache controllers within multi-client memory subsystems as part of their advanced system on a chip (SoC) designs. The ideal candidate will possess extensive ASIC design experience, particularly in memory systems and cache architectures
Job Summary
The role involves designing and developing hardware for cache subsystems within high-performance system on a chip architectures.
Candidates will explore critical trade-offs between system performance, area, and power consumption while defining cache micro-architectures.
The position requires close collaboration with physical design teams to achieve timing closure for the cache subsystem.
Matching Summary
Match Score: 85
Apple is seeking an experienced Asic Design Engineer to work on high-performance cache controllers within multi-client memory subsystems as part of their advanced system on a chip (SoC) designs. The ideal candidate will possess extensive ASIC design experience, particularly in memory systems and cache architectures.
Salary
Not specified; Not specified; Not specified
Skills & Requirements
Must-have
10+ years ASIC design experience
RTL design and micro-architecture definition
Multi-processor cache coherence protocols
PPA analysis for performance power area
Cache subsystem design background
Nice-to-have
High-performance coherent memory systems knowledge