Candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing
Job Summary
Candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.
Candidate will be involved in static timing analysis, providing/deriving interface timing constraints to partitions and doing final timing signoff.
Candidate will also work closely with design and architecture team for timing convergence analysis and will also work with physical design team for timing closure.
Matching Summary
Candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.
Skills & Requirements
Must-have
Static Timing Analysis
Interface Timing Constraints
Timing Signoff
FPGA/SoC Timing
Primetime/PTPX
TCL, Python
Nice-to-have
Communication skills
Problem solving skills
Analytical skills
Key Requirements
7+ Years’ experience timing closure and signoff
BE/MS/Phd in Electronics/Electrical Engineering
Experience in timing signoff in 10nm or lower technology
Proficient in physical design industry standard EDA tools