Architect, develop, and deliver a comprehensive verification strategy and methodology that scales seamlessly from IP through subsystems to SoC-level verification
Job Summary
Architect, develop, and deliver a comprehensive verification strategy and methodology that scales seamlessly from IP through subsystems to SoC-level verification.
Collaborate closely with architecture, design, and software teams from initial product definition and specification reviews through implementation, bringup, and productization phases.
Champion innovation across simulation, formal, and accelerated verification methodologies; develop and evaluate new ML-based flows and hybrid software frameworks.
Matching Summary
Architect, develop, and deliver a comprehensive verification strategy and methodology that scales seamlessly from IP through subsystems to SoC-level verification.
Skills & Requirements
Must-have
advanced DV methodologies and tools
interconnect protocols, cache coherency
memory architecture, software integration
UVM, ABV, and co-simulation
SystemVerilog/UVM, C/C++, Python
Nice-to-have
ML-based flows and hybrid software frameworks
setting standards for technical excellence
mentoring and developing verification engineers
Key Requirements
14+ years of relevant experience in design verification
BS/MS in Electrical Engineering, Computer Science, or related field
extensive background in IP DV
demonstrated experience in subsystem and SoC-level verification
Proven deep expertise in interconnects, caches, and memory subsystems
multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL
memory management (MMUs), cache coherency models
verification of global functions including debug, trace, clock & power management, RAS, QoS, and security features
Strong background in simulation-based verification methodologies
proficiency in low-power verification techniques
HDL/verification languages, and industry-standard EDA tools
Advanced hands-on coding proficiency
established track record of developing and delivering highly configurable and reusable verification collateral
Demonstrated experience collaborating with formal verification and emulation teams