Asic Engineering Technical Leader

Cisco UK

Armenia
Rtl-to-gds physical design
Signoff methodologies
Fusion compiler or innovus
Join the Physical Design CAD & Methodology Team—a senior technical group responsible for defining, scaling, and sustaining RTL-to-GDS Physical Design implementation and signoff methodologies across complex ASIC programs

Job Summary

  • Join the Physical Design CAD & Methodology Team—a senior technical group responsible for defining, scaling, and sustaining RTL-to-GDS Physical Design implementation and signoff methodologies across complex ASIC programs.
  • As a Physical Design Flow & Methodology Technical Leader, you will provide technical leadership in defining, developing, and maintaining scalable, signoff-robust Physical Design flows from synthesis handoff through final GDS delivery.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.

Matching Summary

Join the Physical Design CAD & Methodology Team—a senior technical group responsible for defining, scaling, and sustaining RTL-to-GDS Physical Design implementation and signoff methodologies across complex ASIC programs.

Skills & Requirements

Must-have

  • RTL-to-GDS Physical Design
  • signoff methodologies
  • Fusion Compiler or Innovus
  • PrimeTime (MCMM STA)
  • scripting and automation (Tcl, Python, Shell)

Nice-to-have

  • enterprise-scale PD flows
  • power integrity signoff
  • advanced process nodes
  • mentoring engineers
  • high attention to detail

Key Requirements

  • 8+ years of experience in ASIC Physical Design
  • University degree in Electrical Engineering, Computer Engineering, or related field
  • Deep hands-on experience with Physical Design and signoff tools
  • Expert-level understanding of RTL-to-GDS Physical Design and signoff flow

Work Rights

Not specified

Tailored Resume

Cover Letter