Principal Validation Lead

Marvell

Base: $150,680 - $225,700 py; bonus/equity: not sp...
Not specified
8+ years industry experience in silicon validation
Hands-on lab work with oscilloscopes and protocol analyzers
Expertise in cxl 2.0/3.x, pcie gen4/5/6, ddr4/5, hbm, or serdes
Marvell is seeking a Principal Validation Lead to oversee lab validation strategies for advanced ASIC/SoC products, focusing on high-speed interfaces such as CXL, PCIe, and DDR. The ideal candidate will have extensive experience in silicon validation, technical leadership, and lab automation

Job Summary

  • This role combines hands-on silicon bring-up and debug with technical leadership of validation activities across design, DFT, firmware, and product/test engineering.
  • The successful candidate will define overall validation strategy and test plans for ASIC/SoC devices covering functionality, performance, power, margining, and interoperability.
  • Marvell offers comprehensive benefits including an employee stock purchase plan, family support programs, robust mental health resources, and recognition awards.

Matching Summary

Match Score: 85

Marvell is seeking a Principal Validation Lead to oversee lab validation strategies for advanced ASIC/SoC products, focusing on high-speed interfaces such as CXL, PCIe, and DDR. The ideal candidate will have extensive experience in silicon validation, technical leadership, and lab automation.

Salary

Base: $150,680 - $225,700 per annum; Bonus/Equity: Not specified; Benefits: Employee stock purchase plan, family support, mental health resources, recognition awards

Skills & Requirements

Must-have

  • 8+ years industry experience in silicon validation
  • Hands-on lab work with oscilloscopes and protocol analyzers
  • Expertise in CXL 2.0/3.x, PCIe Gen4/5/6, DDR4/5, HBM, or SerDes
  • Scripting skills in Python, TCL, shell, or MATLAB
  • Proven experience leading bring-up of complex ASIC/SoC products

Nice-to-have

  • Experience leading small validation teams on multi-site projects
  • Familiarity with DFT features like scan, BIST, and JTAG
  • Knowledge of signal integrity and power integrity concepts
  • Master's degree in Electrical or Computer Engineering

Key Requirements

  • Bachelor's degree in Electrical Engineering or related field
  • Eligibility to access export-controlled information under US law
  • Demonstrated ability to drive cross-functional debug and closure

Work Rights

Must be eligible to access export-controlled information (US citizens, lawful permanent residents, or protected individuals)

Tailored Resume

Cover Letter