The role focuses on developing production-grade physical design flows and methodologies for complex SoC architectures rather than just block implementation
Job Summary
The role focuses on developing production-grade physical design flows and methodologies for complex SoC architectures rather than just block implementation.
Engineers will utilize advanced EDA tools like Synopsys Fusion Compiler and Cadence Innovus to handle partitioning, placement, routing, and signoff for chip-top level designs.
Candidates are expected to drive innovation by deploying new EDA capabilities and optimizing PPA metrics across multiple projects and process nodes.
Matching Summary
The role focuses on developing production-grade physical design flows and methodologies for complex SoC architectures rather than just block implementation.