Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs
Job Summary
Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Supports SoC customers to ensure high-quality integration and verification of the IP block.
Matching Summary
Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Skills & Requirements
Must-have
IC validation methodologies
RTL coding
logic design
simulation
design integrity
SoC integration
Nice-to-have
FPGA architecture knowledge
programming languages experience
high speed test equipment
Key Requirements
IC validation methodologies
test & measurements
Verilog/System Verilog
Python, tcl, C-programming, VBA, HTML
ATE tester, oscilloscope, signal generator, power supply